MIPS is back, but this time the company is bringing processors to market based on the RISC-V open instruction set architecture, rather than the MIPS architecture the chip designer is synonymous with.
The current incarnation* of MIPS proclaimed its entry to the RISC-V market with a preview of the first products in its new eVocore processor line, which initially comprises two multiprocessor IP cores, the eVocore P8700 and I8500.
MIPS said that the new processors are designed for high-performance, real-time compute applications such as networking, datacenter, and the automotive industry.
To deliver on this goal, the eVocore IP cores was developed around scalability. MIPS said it aims to allow customers to specify custom chip configurations that combine coherent clusters of the multi-threaded, multi-core CPUs to match their power and performance requirements.
Custom configurations might also extend to other types of CPU core, with MIPS stating that it has designed the new cores to support heterogeneous combinations of eVocore processors and other accelerators. A Coherence Manager is part of the design, and this maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.
The RISC-V architecture also provides for customization in the form of user defined instructions (UDIs), and MIPS said this would be useful in many high-end applications, while also keeping full compatibility with standard RISC-V development tools and software libraries.
MIPS is keeping some details close to its chest at the moment, but the eVocore P8700 is branded as the "superscalar performance" design, while the eVocore I8500 carries the tagline of "best-in-class performance efficiency."
To deliver on its superscalar performance, MIPS says the eVocore P8700 features a deep instruction pipeline ..
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